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| 1CY7C1041BNV33 CY7C1041BNV33 256K x 16 Static RAM Features * High speed -- tAA = 12 ns * Low active power -- 612 mW (max.) * Low CMOS standby power (Commercial L version) -- 1.8 mW (max.) * 2.0V Data Retention (660 W at 2.0V retention) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features Functional Description The CY7C1041BNV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1041BNV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram INPUT BUFFER Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 256K x 16 ARRAY 1024 x 4096 I/O0 - I/O7 I/O8 - I/O15 COLUMN DECODER BHE WE CE OE BLE A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 ROW DECODER Cypress Semiconductor Corporation Document #: 001-06434 Rev. ** A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 SENSE AMPS * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised February 1, 2006 [+] Feedback CY7C1041BNV33 Selection Guide -12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Comm'l Ind'l Com'l/Ind'l Com'l L 12 190 8 0.5 -15 15 170 190 8 0.5 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[1] .... -0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] ....................................-0.5V to VCC + 0.5V DC Input Voltage[1] ................................ -0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 3.3V 0.3V Electrical Characteristics Over the Operating Range -12 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Leakage Current Output Leakage Current VCC Operating Supply Current GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Comm'l Ind'l Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -1 -1 Min. 2.4 0.4 VCC+0.5 0.8 +1 +1 190 40 8 0.5 2.2 -0.5 -1 -1 Max. Min. 2.4 0.4 VCC+0.5 0.8 +1 +1 170 190 40 8 0.5 -15 Max. Unit V V V V mA mA mA mA mA mA mA Automatic CE Power-Down Max. VCC, CE > VIH Current --TTL Inputs VIN > VIH or VIN < VIL, f = fMAX Automatic CE Power-Down Max. VCC, CE > VCC - 0.3V, Com'l/Ind'l Current --CMOS Inputs VIN > VCC - 0.3V,or Com'l L VIN < 0.3V, f = 0 Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF AC Test Loads and Waveforms 3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 351 R1 317 THEVENIN EQUIVALENT 167 OUTPUT 1.73V ALL INPUT PULSES 3.3V 90% GND Rise time: 1 V/ns 10% 90% 10% Fall time: 1 V/ns (b) (a) Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "Instant On" case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06434 Rev. ** Page 2 of 8 [+] Feedback CY7C1041BNV33 Switching Characteristics[4] Over the Operating Range -12 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z CE LOW to Low Z [5, 6] [6] -15 Max. Min. 15 12 15 3 12 6 15 7 0 6 7 3 6 7 0 12 6 15 7 0 6 7 15 12 12 0 0 12 8 0 3 6 7 12 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. 12 3 0 3 0 CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z [7, 8] 0 Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [6] 12 10 10 0 0 10 7 0 3 10 WE LOW to High Z[5, 6] Byte Enable to End of Write Data Retention Characteristics Over the Operating Range (For L version only) Parameter VDR ICCDR tCDR tR[9] [3] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions[10] VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Min. 2.0 Max. 330 Unit V A ns ns 0 tRC Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 9. tr < 3 ns for the -12 and -15 speeds. 10. No input may exceed VCC + 0.5V. Document #: 001-06434 Rev. ** Page 3 of 8 [+] Feedback CY7C1041BNV33 Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE HIGH IMPEDANCE DATA OUT Notes: 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-06434 Rev. ** Page 4 of 8 [+] Feedback CY7C1041BNV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Notes: 14. Data I/O is high-impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06434 Rev. ** Page 5 of 8 [+] Feedback CY7C1041BNV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8-I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Mode Power Down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1041BNV33-12VXC CY7C1041BNV33L-12VXC CY7C1041BNV33L-12VC CY7C1041BNV33L-12ZC CY7C1041BNV33L-12ZXC CY7C1041BNV33-15VXC CY7C1041BNV33L-15VXC CY7C1041BNV33L-15ZXC CY7C1041BNV33-15VXI Package Diagram 51-85082 51-85082 51-85082 51-85087 51-85087 51-85082 51-85082 51-85087 51-85082 Package Type 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 44-Pin TSOP II Z44 (Pb-free) 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Lead (400-Mil) Molded SOJ (Pb-free) 44-Pin TSOP II Z44 (Pb-free) 44-Lead (400-Mil) Molded SOJ (Pb-free) Operating Range Commercial 15 Commercial Industrial Please contact local sales representative regarding availability of these parts. Document #: 001-06434 Rev. ** Page 6 of 8 [+] Feedback CY7C1041BNV33 Package Diagrams 44-Lead (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-Pin TSOP II (51-85087) 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06434 Rev. ** Page 7 of 8 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1041BNV33 Document History Page Document Title: CY7C1041BNV33 256K x 16 Static RAM Document Number: 001-06434 REV. ** ECN NO. 423877 Issue Date See ECN Orig. of Change NXR New Data Sheet Description of Change Document #: 001-06434 Rev. ** Page 8 of 8 [+] Feedback |
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